The present disclosure relates to variable resistive memory devices and operating methods. More particularly, the present disclosure relates to variable resistive memory devices having a hierarchical wordline structure.
As the demands of high density and low power consumption continue to increase in memory devices, a new generation of memory devices has recently been introduced. Criteria for the new generation of memory devices include the nonvolatile characteristic for low power consumption, and easy scalability for high density. There have been several types of new generation memory devices, including Phase change Random Access Memory (“PRAM”), Resistive Random Access Memory (“RRAM”), and Magnetic Random Access Memory (“MRAM”).
As shown in FIG. 1a, a unit memory cell is indicated generally by the reference numeral 10. The memory cell 10 includes a bitline (“BL”) 18, a variable resistive material or part 12 connected to the BL, a switching element 14 connected to the variable resistive part, and a wordline (“WL”) 16 connected to the switching element, where the switching element may be a transistor or a diode.
Depending on the variable resistive material, a memory device may be one of PRAM, RRAM or MRAM types. If the variable resistive material is defined by a lower electrode, an upper electrode, and a phase change material between the lower and upper electrodes, then the memory device is PRAM. If the variable resistive material is defined by a lower electrode, an upper electrode, and a Complex Metal Oxide (“CMO”) material between the lower and upper electrodes, then the memory device is RRAM. If the variable resistive material is defined by lower and upper electrodes of ferroelectric material with an insulating material between them, the memory device is MRAM. A common characteristic of these three types of memory devices is that current flows from a bitline to a wordline or vice versa when a Write operation or a Read operation occurs. For simplicity of explanation, it may be hereinafter assumed that the variable resistive material is a phase change material, but the concepts extend to the other types of new generation memory devices as well.
Turning to FIG. 1b, a memory is indicated generally by the reference numeral 20. The memory 20 includes at least one cell array 22 having a plurality of memory cells 10 of FIG. 1a, a sense amplifier 24 connected to the cell 10 for providing a read current, and a write driver 26 connected to the cell 10 for providing a write current, which may be either a reset or a set current.
During a Write operation, the write current flows from write driver 26 towards the WL 16. If the write data is “1”, a reset current flows from the BL 18 of FIG. 1a to the WL 16 of FIG. 1a through the unit memory cell 10. If the write data is “0”, a set current flows from the BL to the WL through the unit memory cell 10. The reset current is larger than the set current.
During a Read operation, the read current flows from the sense amplifier 24 towards the WL. The sense amplifier detects the read current and amplifies the read current. The amount of current is dependent on a voltage difference between the BL and the WL.
Turning now to FIG. 2, a memory device is indicated generally by the reference numeral 100. The memory device 100 includes first and second memory sectors SEC1 and SEC2, memory blocks BLK1, BLK2, BLK3 and BLK4, a first main wordline driver 211 connected to a main wordline (“MWL”) in the first sector SEC1, and a second main wordline driver 212 connected to a MWL in the second sector SEC2. Each block of each sector includes a sub-wordline driver 221 connected to the sub-wordline (“SWL”) for the sector. Each memory block of the first sector includes a local bitline selection part 230, and each memory block of the second sector includes a local bitline selection part 220. A plurality of write driver and sense amplifier units 240 connect to a corresponding number of global bitlines (“GBL”), which connect to each block.
For an exemplary Write operation of the memory device 100, the dotted lines of FIG. 2 indicate non-activated lines and the solid lines indicate the activated lines. During this Write operation, one MWL in one memory sector (here, SEC1) is activated by a main wordline driver (here, 211). Each sub-wordline driver 221 of the memory blocks in SEC1 drives the SWL of the sector to reach VSS. The local bitline selecting parts 230 in SEC1 connect each local bitline (“LBL”) in each memory block to a corresponding global bitline (“GBL”) for that column or bit position. Thus, a voltage of the GBL delivered by the write driver is transferred to the LBL in each memory block in SEC1. Therefore, a write current due to the voltage difference between LBL and SWL flows from each LBL to the SWL through the variable resistive material in each memory cell. Due to the amount of the write current, the variable resistive material exhibits either high resistance or low resistance.
Unfortunately, since the write current can flow to one SWL through all of the memory cells connected to the one SWL, a voltage of the SWL rises. Due to this rise of the voltage of the SWL, the voltage difference between a bitline and the SWL is reduced and a desirable write current from a given LBL to the SWL may not flow. This can cause a Write operation to fail. In addition, a Read operation can fail for similar reasons.